MSTIR=Val_0x0, RXFIR=Val_0x0, RXUIR=Val_0x0, TXOIR=Val_0x0, RXOIR=Val_0x0, TXEIR=Val_0x0
Raw Interrupt Status Register
| TXEIR | Transmit FIFO Empty Raw Interrupt Status. 0 (Val_0x0): Transmit FIFO Empty interrupt is not active prior masking 1 (Val_0x1): Transmit FIFO Empty interrupt is active prior to masking |
| TXOIR | Transmit FIFO Overflow Raw Interrupt Status. 0 (Val_0x0): Transmit FIFO Overflow interrupt is not active prior masking 1 (Val_0x1): Transmit FIFO Overflow interrupt is active prior to masking |
| RXUIR | Receive FIFO Underflow Raw Interrupt Status. 0 (Val_0x0): Receive FIFO Underflow interrupt is not active prior masking 1 (Val_0x1): Receive FIFO Underflow interrupt is active prior to masking |
| RXOIR | Receive FIFO Overflow Raw Interrupt Status. 0 (Val_0x0): Receive FIFO Overflow interrupt is not active prior masking 1 (Val_0x1): Receive FIFO Overflow interrupt is active prior to masking |
| RXFIR | Receive FIFO Full Raw Interrupt Status. 0 (Val_0x0): Receive FIFO Full interrupt is not active prior masking 1 (Val_0x1): Receive FIFO Full interrupt is active prior to masking |
| MSTIR | Multi-Master Contention Raw Interrupt Status. This bit field is not present if the SPI is configured as a serial slave device. 0 (Val_0x0): Multi-Master Contention interrupt is not active prior masking 1 (Val_0x1): Multi-Master Contention interrupt is active prior to masking |